CURPIPE=Others, BIGEND=0, DCLRM=0, DREQE=0, MBW=0, RCNT=0, REW=0
D1FIFO Port Select Register
| CURPIPE | FIFO Port Access Pipe Specification 0 (0x0): Default Control Pipe 0 (Others): Setting prohibited 1 (0x1): Pipe 1 2 (0x2): Pipe 2 3 (0x3): Pipe 3 4 (0x4): Pipe 4 5 (0x5): Pipe 5 6 (0x6): Pipe 6 7 (0x7): Pipe 7 8 (0x8): Pipe 8 9 (0x9): Pipe 9 |
| BIGEND | FIFO Port Endian Control 0 (0): Little endian 1 (1): Big endian |
| MBW | FIFO Port Access Bit Width 0 (0): 8-bit width 1 (1): 16-bit width |
| DREQE | DMA/DTC Transfer Request Enable 0 (0): Disable DMA/DTC transfer request 1 (1): Enable DMA/DTC transfer request |
| DCLRM | Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read 0 (0): Disable auto buffer clear mode 1 (1): Enable auto buffer clear mode |
| REW | Buffer Pointer Rewind 0 (0): Do not rewind buffer pointer 1 (1): Rewind buffer pointer |
| RCNT | Read Count Mode 0 (0): Clear DTLN[8:0] bits in (CFIFOCTR.DTLN[8:0], D0FIFOCTR.DTLN[8:0], D1FIFOCTR.DTLN[8:0]) when all receive data is read from DnFIFO (after read of a single plane in double buffer mode) 1 (1): Decrement DTLN[8:0] bits each time receive data is read from DnFIFO |